125 lines
4.4 KiB
ArmAsm
125 lines
4.4 KiB
ArmAsm
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/**
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******************************************************************************
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* @file startup_stm32f401xc.s
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* @author MCD Application Team
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* @version V2.4.2
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* @date 13-November-2015
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* @brief STM32F401xCxx Devices vector table for GCC based toolchains.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2015 STMicroelectronics
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Check for magic code at the end of SRAM to detemine whether to jump to DFU */
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ldr r0, =0x2000FFF0 // End of SRAM for your CPU
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ldr r1, =0xDEADBEEF
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ldr r2, [r0, #0]
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str r0, [r0, #0] // Invalidate
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cmp r2, r1
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beq Jump_To_DFU
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/* Original Reset_Handler code */
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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bx lr
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Jump_To_DFU:
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ldr r0, =0x40023844 // RCC_APB2ENR
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ldr r1, =0x00004000 // ENABLE SYSCFG CLOCK
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str r1, [r0, #0]
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ldr r0, =0x40013800 // SYSCFG_MEMRMP
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ldr r1, =0x00000001 // MAP ROM AT ZERO
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str r1, [r0, #0]
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ldr r0, =0x1FFF0000 // ROM BASE
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ldr sp, [r0, #0] // SP @ +0
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ldr r0, [r0, #4] // PC @ +4
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bx r0
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.size Reset_Handler, .-Reset_Handler
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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